Embedded chip substrate and fabrication method thereof

ABSTRACT

An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 97127864, filed on Jul. 22, 2008. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a substrate and a fabricationmethod thereof. More particularly, the present invention relates to anembedded chip substrate and a fabrication method thereof.

2. Description of Related Art

With recent progress of electronic technologies, electronic productsthat are more user-friendly and with better functions are continuouslydeveloped. Further, these products are designed to satisfy requirementsfor lightness, slimness, shortness, and compactness. In a housing of theelectronic product, a circuit board is often disposed for carryingvarious electronic elements. The electronic elements occupy the carryingarea on the circuit board. Hence, when the number of the electronicelements increases, the carrying area on the circuit board is requiredto be extended. As such, the area occupied by the circuit board isinevitably increased as well, which deteriorates miniaturization of theelectronic products. In addition, the circuit boards used in chippackages also encounter the similar issue.

SUMMARY OF THE INVENTION

The present invention is directed to an embedded chip substrate in whicha chip does not occupy a carrying area of a circuit board.

The present invention further provides a fabrication method of anembedded chip substrate. A chip in the embedded chip substrate formed byconducting said fabrication method does not occupy a carrying area of acircuit board.

In the present invention, an embedded chip substrate including a firstinsulation layer, a core layer, a chip, a second insulation layer, afirst circuit layer, and a second circuit layer is provided. The corelayer is disposed on the first insulation layer and has an opening thatexposes a portion of the first insulation layer. The chip is adheredinto a recess formed by the opening and the first insulation layer. Thesecond insulation layer is disposed on the core layer for covering thechip. The first circuit layer is disposed at the outer side of the firstinsulation layer, and the first insulation layer is located between thefirst circuit layer and the core layer. The second circuit layer isdisposed at the outer side of the second insulation layer, and thesecond insulation layer is located between the second circuit layer andthe core layer. The first circuit layer is electrically connected to thesecond circuit layer that is electrically connected to the chip.

In an embodiment of the present invention, a material of the firstinsulation layer includes a two-stage curable compound.

In an embodiment of the present invention, a material of the secondinsulation layer includes a two-stage curable compound.

In an embodiment of the present invention, the embedded chip substratefurther includes a bottom adhesion layer that is disposed on the firstinsulation layer in the recess and located between the chip and thefirst insulation layer.

In an embodiment of the present invention, the embedded chip substratefurther includes a side wall adhesion layer that is disposed between theinner side wall of the recess and the side wall of the chip.

In an embodiment of the present invention, the embedded chip substratefurther includes a side wall adhesion layer that is disposed between theinner side wall of the recess and the side wall of the chip.

In an embodiment of the present invention, the first insulation layer isextended between the inner side wall of the recess and the side wall ofthe chip.

In an embodiment of the present invention, the embedded chip substratefurther includes a plurality of conductive blind vias penetrating thesecond insulation layer and electrically connected to the second circuitlayer and the chip.

In an embodiment of the present invention, the embedded chip substratefurther includes a plurality of conductive through holes penetrating thesecond insulation layer, the core layer, and the first insulation layerand electrically connected to the first circuit layer and the secondcircuit layer.

In an embodiment of the present invention, the core layer furtherincludes a core dielectric layer and two core circuit layers. The twocore circuit layers are respectively disposed at opposite sides of thecore layer.

In an embodiment of the present invention, the embedded chip substratefurther includes two build-up structures respectively disposed at theouter side of the second insulation layer and the outer side of thefirst insulation layer, and a plurality of solder pads are respectivelylocated at the outer sides of the two build-up structures.

In an embodiment of the present invention, the embedded chip substratefurther includes two solder mask layers respectively disposed at theouter sides of the build-up structures and respectively exposing thecorresponding solder pads.

In the present invention, a fabrication method of an embedded chipsubstrate is further provided hereinafter. First, a core layer that hasan opening is provided. Next, a first insulation layer and a firstconductive layer are provided. The first conductive layer is disposed onthe first insulation layer. The core layer is then disposed on the firstinsulation layer that is located between the core layer and the firstconductive layer. After that, a chip is adhered into a recess formed bythe opening and the first insulation layer. Thereafter, a secondinsulation layer and a second conductive layer are provided. The secondconductive layer is disposed on the second insulation layer. The secondinsulation layer is then disposed on the core layer. The secondinsulation layer is located between the core layer and the secondconductive layer and covers the recess. Afterwards, the first conductivelayer, the first insulation layer, the core layer, the second insulationlayer, and the second conductive layer are laminated. Next, the firstconductive layer and the second conductive layer are respectivelypatterned, so as to form a first circuit layer and a second circuitlayer. The first circuit layer is electrically connected to the secondcircuit layer, and the second circuit layer is electrically connected tothe chip.

In an embodiment of the present invention, the fabrication method of theembedded chip substrate further includes forming a plurality ofconductive blind vias penetrating the second insulation layer before thefirst conductive layer is patterned, such that the chip is electricallyconnected to the second conductive layer.

In an embodiment of the present invention, the fabrication method of theembedded chip substrate further includes forming a plurality ofconductive through holes penetrating the second insulation layer, thecore layer, and the first insulation layer after the first conductivelayer and the second conductive layer are patterned, such that the firstcircuit layer is electrically connected to the second circuit layer.

In an embodiment of the present invention, the fabrication method of theembedded chip substrate further includes heating the first insulationlayer in the step of laminating the first conductive layer, the firstinsulation layer, the core layer, the second insulation layer, and thesecond conductive layer, such that the first insulation layer overflowsbetween the side wall of the chip and the inner side wall of the recess.

In an embodiment of the present invention, a method of adhering the chipinto the recess includes disposing a bottom adhesion layer on the firstinsulation layer that is located in the recess and disposing the chip onthe bottom adhesion layer.

In an embodiment of the present invention, the method of adhering thechip into the recess further includes forming a side wall adhesion layerbetween the inner side wall of the recess and the side wall of the chip.

In an embodiment of the present invention, a method of adhering the chipinto the recess includes forming a side wall adhesion layer between theinner side wall of the recess and the side wall of the chip.

In an embodiment of the present invention, the fabrication method of theembedded chip substrate further includes respectively forming a build-upstructure at the outer side of the first insulation layer and the outerside of the second insulation layer. A plurality of solder pads arelocated at the outer sides of the two build-up structures, respectively.

In light of the foregoing, the chip is embedded into the circuit boardaccording to the present invention, and therefore the chip does notoccupy the carrying area of the circuit board.

In order to make the above and other features and advantages of thepresent invention more comprehensible, several embodiments accompaniedwith figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings constituting a part of this specification areincorporated herein to provide a farther understanding of the invention.Here, the drawings illustrate embodiments of the invention and, togetherwith the description, serve to explain the principles of the invention.

FIGS. 1A through 1L are schematic cross-sectional flowchartsillustrating a process of manufacturing an embedded chip substrateaccording to an embodiment of the present invention.

FIGS. 2A and 2B are schematic cross-sectional flowcharts illustrating aprocess of manufacturing an embedded chip substrate according to anotherembodiment of the present invention.

FIG. 3 is a schematic cross-sectional flowchart illustrating a processof manufacturing an embedded chip substrate according to still anotherembodiment of the present invention.

FIGS. 4 and 5 are schematic cross-sectional views illustrating twomodifications of the embedded chip substrate depicted in FIG. 1L.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A through 1L are schematic cross-sectional flowchartsillustrating a process of manufacturing an embedded chip substrateaccording to an embodiment of the present invention. FIGS. 2A and 2B areschematic cross-sectional flowcharts illustrating a process ofmanufacturing an embedded chip substrate according to another embodimentof the present invention. FIG. 3 is a schematic cross-sectionalflowchart illustrating a process of manufacturing an embedded chipsubstrate according to still another embodiment of the presentinvention.

First, referring to FIG. 1A, a core layer 10 is provided. The core layer10 includes a core dielectric layer 12 and two conductive layers 14 thatare disposed at opposite sides of the core dielectric layer 12,respectively. The core dielectric layer 12 can be an insulation board.Additionally, in other embodiments that are not depicted in thedrawings, a multi-layered board can serve as a substitute for the coredielectric layer 12 of the present embodiment. The multi-layered boardcan be composed of multiple circuit layers and multiple insulationlayers alternately arranged.

Next, referring to FIG. 1B, the two conductive layers 14 are patterned,respectively, so as to form two core circuit layers 14 a. After that,referring to FIG. 1C, an opening 16 is formed on the core layer 10.Here, a method of forming the opening 16 includes performing a routingprocess, such as a mechanical drilling process, a punching process, orany other appropriate routing processes.

Thereafter, referring to FIG. 1D, a first insulation layer 110 and afirst conductive layer 120 are provided. The first conductive layer 120is disposed on the first insulation layer 110, and a material of thefirst insulation layer 110 is, for example, a two-state curablecompound. In the present embodiment, a resin coated copper (RCC) can beused to form the first insulation layer 110 and the first conductivelayer 120. After that, the core layer 10 is disposed on the firstinsulation layer 110, and the first insulation layer 110 is locatedbetween the core layer 10 and the first conductive layer 120. Besides,the opening 16 and the first insulation layer 110 together form a recessR.

Afterwards, referring to FIG. 1E, a chip 130 is adhered into the recessR. In the present embodiment, the chip 130 is adhered into the recess Rby disposing a bottom adhesion layer 142 on the first insulation layer110, so as to adhere the chip 130 onto the first insulation layer 110.Additionally, a side wall adhesion layer 144 is formed between the innerside wall of the recess R and the side wall of the chip 130, so as toadhere the chip 130 to the inner side wall of the recess R. Besides, inother embodiments, the chip 130 can also be adhered into the recess Ronly by means of the bottom adhesion layer 142 (as shown in FIG. 2A) orthe side wall adhesion layer 144 (as shown in FIG. 3).

A material of the bottom adhesion layer 142 is, for example, polyimide(PI), or any other appropriate adhesive materials. By contrast, amaterial of the side wall adhesion layer 144 is, for example, epoxyresin, or any other appropriate adhesive materials.

Next, referring to FIG. 1F, a second insulation layer 150 and a secondconductive layer 160 are provided. The second conductive layer 160 isdisposed on the second insulation layer 150. In the present embodiment,the RCC can be used to form the second insulation layer 150 and thesecond conductive layer 160. The second insulation layer 150 is thendisposed on the core layer 10. Here, the second insulation layer 150 islocated between the core layer 10 and the second conductive layer 160and covers the recess R.

After that, referring to FIG. 1G, the first conductive layer 120, thefirst insulation layer 110, the core layer 10, the second insulationlayer 150, and the second conductive layer 160 are laminated. Besides,the first insulation layer 110 can be heated during the lamination.Since the first insulation layer 110 can be made of the two-stagecurable compound, a portion of the first insulation layer 110 overflowsbetween the side wall of the chip 130 and the inner side wall of therecess R.

Thereby, no air or moisture would exist between the side wall of thechip 130 and the inner side wall of the recess R, such that anoccurrence of a popcorn effect can be avoided. Moreover, a material ofthe second insulation layer 150 can also include the two-stage curablecompound, which is conducive to filling up the space between the sidewall of the chip 130 and the inner side wall of the recess R.

According to other embodiments, when the chip 130 is adhered into therecess R only by means of the bottom adhesion layer 142 (as shown inFIG. 2A), the lamination of the first conductive layer 120, the firstinsulation layer 110, the core layer 10, the second insulation layer150, and the second conductive layer 160 and the heating of the firstinsulation layer 110 allow the space between the side wall of the chip130 and the inner side wall of the recess R to be filled with a portionof the first insulation layer 110 (as shown in FIG. 2B). As such, it isnot necessary to fill the space between the side wall of the chip 130and the inner side wall of the recess R with other fillers forpreventing the occurrence of the popcorn effect.

After that, referring to FIG. 1H, a plurality of conductive blind vias Bpenetrating the second insulation layer 150 are formed in the presentembodiment, so as to electrically connect the chip 130 to the secondconductive layer 160. Next, referring to FIG. 11, the first conductivelayer 120 and the second conductive layer 160 are respectivelypatterned, so as to form a first circuit layer 122 and a second circuitlayer 162.

Referring to FIG. 1J, a plurality of conductive through holes Tpenetrating the second insulation layer 150, the core layer 10, and thefirst insulation layer 110 are then formed in the present embodiment, soas to electrically connect the first circuit layer 122 to the secondcircuit layer 162.

Thereafter, referring to FIG. 1K, in the present embodiment, a build-upstructure 170 can be further formed at the outer side of the firstinsulation layer 110 and the outer side of the second insulation layer150, respectively. A plurality of solder pads 172 are respectivelydisposed at the outer sides of the build-up structures 170. Next,referring to FIG. 1L, a solder mask layer 180 is formed on the build-upstructures 170, respectively, so as to expose the corresponding solderpads 172. To avoid the surfaces of the solder pads 172 from beingoxidized, an electrical connection layer 190 can then be formed on thesolder pads 172. Here, the electrical connection layer 190 is, forexample, a Ni/Au composite layer.

The structure of the embedded chip substrate in FIG. 1L is elaboratedhereinafter.

FIGS. 4 and 5 are schematic cross-sectional views illustrating twomodifications of the embedded chip substrate depicted in FIG. 1L.

As shown in FIG. 1L, an embedded chip substrate 200 of the presentembodiment includes a first insulation layer 110, a core layer 10, achip 130, a second insulation layer 150, a first circuit layer 122, anda second circuit layer 162. The first insulation layer 110 is made of atwo-stage curable compound, for example.

The core layer 10 is disposed on the first insulation layer 110 and hasan opening 16 that exposes a portion of the first insulation layer 110.The opening 16 and the first insulation layer 110 together form a recessR where the chip 130 is adhered. In the present embodiment, a bottomadhesion layer 142 is disposed between the chip 130 and the firstinsulation layer 110, and a side wall adhesion layer 144 is disposedbetween the inner side wall of the recess R and the side wall of thechip 130, so as to adhere the chip 130 into the recess R.

Besides, referring to FIG. 4, in other embodiments, the chip 130 can beadhered into the recess R only by means of the bottom adhesion layer142. Note that the first insulation layer 110 can be extended into thespace between the inner side wall of the recess R and the side wall ofthe chip 130, and therefore it is not necessary to fill the space withother fillers for preventing the occurrence of the popcorn effect.Moreover, the material of the second insulation layer 150 can alsoinclude the two-stage curable compound, and thus the second insulationlayer 150 can also be extended into the space between the inner sidewall of the recess R and the side wall of the chip 130 (not shown).Besides, referring to FIG. 5, in other embodiments, the chip 130 can beadhered into the recess R only by means of the side wall adhesion layer144.

As shown in FIG. 1L, the second insulation layer 150 is disposed on thecore layer 10 for covering the chip 130. In addition, the material ofthe second insulation layer 150 can include the two-stage curablecompound. The first circuit layer 122 is disposed at the outer side ofthe first insulation layer 110, and the first insulation layer 110 islocated between the first circuit layer 122 and the core layer 10. Thesecond circuit layer 162 is disposed at the outer side of the secondinsulation layer 150, and the second insulation layer 150 is locatedbetween the second circuit layer 162 and the core layer 10.

In the present embodiment, the first circuit layer 122 and the secondcircuit layer 162 can be electrically connected to each other through aplurality of conductive through holes T penetrating the secondinsulation layer 150, the core layer 10, and the first insulation layer110. The second circuit layer 162 and the chip 130 can be electricallyconnected to each other through a plurality of conductive blind vias Bpenetrating the second insulation layer 150.

Additionally, in the present embodiment, a build-up process can beperformed at the outer side of the second insulation layer 150 and theouter side of the first insulation layer 110 based on actual demands.According to the present embodiment, a build-up structure 170 is formedrespectively at the outer side of the second insulation layer 150 andthe outer side of the first insulation layer 110, and a plurality ofsolder pads 172 are formed at the outer side of each of the built-upstructures 170. Moreover, a solder mask layer 180 is formed respectivelyat the outer sides of the two build-up structures 170 in the presentembodiment, and each of the solder mask layers 180 exposes thecorresponding solder pads 172.

To avoid the surfaces of the solder pads 172 from being oxidized, anelectrical connection layer 190 can be further formed on each of thesolder pads 172. Here, the electrical connection layer 190 is, forexample, a Ni/Au composite layer.

Based on the above, the chip is embedded into the circuit boardaccording to the present invention, and therefore the chip does notoccupy the carrying area on the circuit board. Further, in the aforesaidembodiments, the first insulation layer can be made of the two-stagecurable compound. Thus, when the first conductive layer, the firstinsulation layer, the core layer, the second insulation layer, and thesecond conductive layer are laminated, the first insulation layer can beheated, such that the first insulation layer overflows between the sidewall of the chip and the inner side wall of the recess. Thereby, no airor moisture would exist between the side wall of the chip and the innerside wall of the recess, so as to prevent the occurrence of the popcorneffect.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. An embedded chip substrate, comprising: a first insulation layer; acore layer, disposed on the first insulation layer and having an openingfor exposing a portion of the first insulation layer; a chip, adheredinto a recess formed by the opening and the first insulation layer; asecond insulation layer, disposed on the core layer for covering thechip; a first circuit layer, disposed at the outer side of the firstinsulation layer, the first insulation layer being disposed between thefirst circuit layer and the core layer; and a second circuit layer,disposed at the outer side of the second insulation layer, wherein thesecond insulation layer is located between the second circuit layer andthe core layer, the first circuit layer is electrically connected to thesecond circuit layer, and the second circuit layer is electricallyconnected to the chip.
 2. The embedded chip substrate as claimed inclaim 1, wherein a material of the first insulation layer comprises atwo-stage curable compound.
 3. The embedded chip substrate as claimed inclaim 1, wherein a material of the second insulation layer comprises atwo-stage curable compound.
 4. The embedded chip substrate as claimed inclaim 1, further comprising: a bottom adhesion layer, disposed on thefirst insulation layer in the recess and located between the chip andthe first insulation layer.
 5. The embedded chip substrate as claimed inclaim 4, further comprising: a side wall adhesion layer, disposedbetween the inner side wall of the recess and the side wall of the chip.6. The embedded chip substrate as claimed in claim 1, furthercomprising: a side wall adhesion layer, disposed between the inner sidewall of the recess and the side wall of the chip.
 7. The embedded chipsubstrate as claimed in claim 1, wherein the first insulation layer isextended between the inner side wall of the recess and the side wall ofthe chip.
 8. The embedded chip substrate as claimed in claim 1, furthercomprising: a plurality of conductive blind vias, penetrating the secondinsulation layer and electrically connected to the second circuit layerand the chip.
 9. The embedded chip substrate as claimed in claim 1,further comprising: a plurality of conductive through holes, penetratingthe second insulation layer, the core layer, and the first insulationlayer and electrically connected to the first circuit layer and thesecond circuit layer.
 10. The embedded chip substrate as claimed inclaim 1, wherein the core layer comprises: a core dielectric layer; andtwo core circuit layers, respectively disposed at opposite sides of thecore layer.
 11. The embedded chip substrate as claimed in claim 1,further comprising: two build-up structures, respectively disposed atthe outer side of the second insulation layer and the outer side of thefirst insulation layer, a plurality of solder pads being located at theouter sides of the two build-up structures, respectively.
 12. Theembedded chip substrate as claimed in claim 11, further comprising: twosolder mask layers, respectively disposed at the outer sides of thebuild-up structures and respectively exposing the corresponding solderpads.
 13. A fabrication method of an embedded chip substrate, thefabrication method comprising: providing a core layer that has anopening; providing a first insulation layer and a first conductivelayer, the first conductive layer being disposed on the first insulationlayer; disposing the core layer on the first insulation layer, the firstinsulation layer being located between the core layer and the firstconductive layer; adhering a chip into a recess formed by the openingand the first insulation layer; providing a second insulation layer anda second conductive layer, the second conductive layer being disposed onthe second insulation layer; disposing the second insulation layer onthe core layer, the second insulation layer being located between thecore layer and the second conductive layer and covering the recess;laminating the first conductive layer, the first insulation layer, thecore layer, the second insulation layer, and the second conductivelayer; and respectively patterning the first conductive layer and thesecond conductive layer, so as to form a first circuit layer and asecond circuit layer, wherein the first circuit layer is electricallyconnected to the second circuit layer, and the second circuit layer iselectrically connected to the chip.
 14. The fabrication method of theembedded chip substrate as claimed in claim 13, further comprising:forming a plurality of conductive blind vias penetrating the secondinsulation layer before the first conductive layer is patterned, suchthat the chip is electrically connected to the second conductive layer.15. The fabrication method of the embedded chip substrate as claimed inclaim 13, further comprising: forming a plurality of conductive throughholes penetrating the second insulation layer, the core layer, and thefirst insulation layer after the first conductive layer and the secondconductive layer are patterned, such that the first circuit layer iselectrically connected to the second circuit layer.
 16. The fabricationmethod of the embedded chip substrate as claimed in claim 13, furthercomprising: heating the first insulation layer in the step of laminatingthe first conductive layer, the first insulation layer, the core layer,the second insulation layer, and the second conductive layer, such thatthe first insulation layer overflows between the side wall of the chipand the inner side wall of the recess.
 17. The fabrication method of theembedded chip substrate as claimed in claim 13, wherein a method ofadhering the chip into the recess comprises: disposing a bottom adhesionlayer on the first insulation layer that is located in the recess; anddisposing the chip on the bottom adhesion layer.
 18. The fabricationmethod of the embedded chip substrate as claimed in claim 17, whereinthe method of adhering the chip into the recess further comprises:forming a side wall adhesion layer between the inner side wall of therecess and the side wall of the chip.
 19. The fabrication method of theembedded chip substrate as claimed in claim 13, wherein a method ofadhering the chip into the recess comprises: forming a side walladhesion layer between the inner side wall of the recess and the sidewall of the chip.
 20. The fabrication method of the embedded chipsubstrate as claimed in claim 13, further comprising: respectivelyforming a build-up structure at the outer side of the first insulationlayer and the outer side of the second insulation layer, a plurality ofsolder pads being located at the outer sides of the two build-upstructures, respectively.